A circuit scale of LSI (Large Scale Integrated Circuit) becomes large year by year, and furthermore it is requested to make a design time short. Moreover, an electronic circuit, whose circuit operation can be described by a program, such as FPGA (Field Programmable Gate Alley) is prevailing. As a result, it becomes a general way nowadays to design a logic circuit by use of not a circuit diagram but a hardware description language (HDL: Hardware Description Language).
In verifying a logic circuit which is written in the hardware description language, code coverage (code coverage ratio) is used as an index of test coverage properties or a degree of verification accuracy. The code coverage represents a ratio of executed codes, among codes (instruction sentence, branch, path, and the like)
Particularly, in the case of verifying the logic circuit which is written in the hardware description language, it is a general way to carry out a simulation test before carrying out an actual test. As an index indicating degree of how much is carried out for the simulation test, the code coverage is used.
As a related art, a patent document 1 discloses an art which, when verifying a function of a logic circuit of a system LSI, by detecting an unexpected-operation test pattern, prevents the code coverage from being missed A patent document 2 discloses an art which, when verifying a LSI design, for an emulation whose code coverage cannot be measured directly, transforms the code coverage into the assertion language which is a description language for verifying a LSI function, and measures the code coverage.
A patent document 3 discloses a test simplifying circuit which outputs a signal, which is outputted from an observation point arranged on a tested circuit, to a compression circuit, and connects an output of the compression circuit with a flip-flop. A patent document 4 discloses an LSI design verifying apparatus which enables to measure the code coverage by storing a signal connection relation in a common database and using the signal connection relation. A patent document 5 discloses a circuit design system which determines an observation point by extracting a candidate which may be caused failure.
A patent document 6 discloses a test method which improves the test coverage properties by use of the assertion checker for monitoring the test. A patent document 7 discloses a verification apparatus which extracts a coverage point group from a hardware program on the basis of semantic interpretation, and carries out a logical simulation by use of the coverage point group. Non-patent documents 1 to 3 explain terminologies of the hardware description language (HDL), the code coverage and the assertion language.